Processes, Memory Map, Protected Systems, ARM systems with MPU, memory Protection Unit (MPU)

[noise] [noise] Hello friends, [noise] welcome you all to the [noise] section [noise] 37 of ARM Based Development [noise] ok [noise] We are going to take a [noise] a different topics [noise] today and maybe subsequent [noise] two lectures, [vocalized-noise] its all about [noise] how memory is managed [noise] ok, which are memory hierarchy and cache memories organization in detail. So, for now we are going to see, [noise] two [noise] important [noise] functionalities ok related to memory one is memory protection, [noise] other one is the virtual memory ok. So, [noise] take a story about virtual memory and MMU later, today’s focus will be on memory protection units ok [noise] let us see got it [noise] So, in this [noise] discussion we will be covering about little bit I will give a overview of process when context switch, they have a touched upon this in subsequent in earlier chapter ah it is a appropriate to just talk about it little bit before we get into ah processors and memory protection. So, then we will talk about what are protect protected systems and why do we need a system which has got protection built into it and then, we will go into detail of MPU ok and then we will see how MPU can be considered. Now, just to give you ah a overview ok [noise] you Let me choose a nice color [noise] say we saw ARM processor, then I really we touched upon coprocessors ok [noise] and then we saw memory hierarchy [noise] and then some memory controllers [noise] we do main memory, which I am assume it to be outside as a soc and [noise] memory controller [noise] connecting each other; [noise] and then we have [noise] address bus, [noise] going there [noise] and the data bus [noise] is coming to the [noise] coprocessor here what we are saying is that is not VFP ok [noise] an example So, and then yesterday, ah one of the previous classes we talked about cache which came in between a memory controller and (Refer Time: 03:05) memory now we have two topics to the same one is memory protection unit and memory management unit. [noise] Now this is not the focus now this is a focus memory protection unit. So, one thing that you you should remember is memory protection unit functionalities [noise] are built into the MMU if MMU present in the system ok. So, there will not be a system with both MPU and MMU as a separate each entities, this functionality will be observed by MMU and MMU is actually having a MPU functionality also built easy So, if so I say the system has an MMU, that maintaining lets it be assumed m at MPU functionalities are there. I am not a told what is the functionalities of MPU, but then its this different issues [vocalized-noise] remember. [noise] Now because in our discussion today we are going to talk about, [noise] ah memory protection unit; so MPU is not MMU is not there ok. Let me remove ah right, now [noise] a moment cache also to just ah [vocalized-noise] not MPU is there [noise] ok [noise] only MPU [noise]; that means, there is no MMU in that case what happens is [noise] the address bus that goes into the MPU is also going into the memory ok this is address bus [noise] ok [noise] Because there is no logical memory or [noise] physical memory virtual memory those concepts [noise] are not there [noise] when we are talking about MPU as a independent unit in the system ok. Again an option of having an

MPU or MMU is a designers choice ok. So, if [noise] a system what you build ok, that is not mean virtual memory support [noise], but it needs the memory protection unit support only then, the choice will be to take only this module [noise] and do not bring in a virtual memory at all; [noise] in the case what happens the memory addresses what the processor gives out is directly going to the memory [noise] ok and accessing that So, the physical memory is what processors need ok [noise] processor or any processors running in the list in the processor [noise] does not have any other virtual memory system in the in its ah execution. So, whatever is a memory it sees its a mm the memory management [vocalized-noise] the [vocalized-noise] than the main memory [noise] area. So, if suppose you should have got one day no ah 256 MB [noise] of main memory then the [vocalized-noise] the program space also will be only limited to [vocalized-noise]. So, you have been I have to write everything, only considering that there are [vocalized-noise] there is only a 256 MB of space in the system and all the program should fall within that You know whatever we are deciding about core or data or stack what very simple we should all be restricted to only the physical memory available in the system, there is no MMU to transfer it to another unit collected virtual memory space may be bigger and the actual physical memory what you have in it this will be smaller. So, that option is not there So, we have to keep in mind that when we are talking about only MPU in isolation, we do not have a MMU present in the system and there is no virtual memory concept here ok. So, we can build a system like that all Now, we may wonder [noise] who is providing this MPU and [noise] MMU, whatever I am discussing now it all provided by ARM [noise] see ARM does not only some give you ip of the processor core ok. It also gives as we saw that cache [noise] controller and a cache you can core which we can build and consider using the controller; [noise] and it also provides coprocessor and VFP and it also has a bus standard which I will be talking about in subsequent chapter [noise]. So, its also provides you the necessary [noise] now IP along with all the not text, but testing purpose also it gives you. So, many support in the while providing nineties also. So, bus is there may [vocalized-noise] it provides all the ingredients main ingredients for building the soc [noise] So, MPU is also one of the coprocessors ok [noise] Now when I say MPU is a coprocessor ok, [noise] you may immediately [noise] remember me saying that the coprocessor will not have access to address bus right. I mentioned it earlier let me clarify what I meant by that ok, maybe this color is better still in case of functionality when we want to build in a new functionality you want to add we you talked about vector for floating planning processor which is the coprocessor it mean is the some access to memory also Because it has a keep its data here and then it will be doing a protein kind memory during that I am said that ARM only manages the memory space and it will only generate there and MMU also they are all coprocessors ok. But there are number is 15 in the specific tool coprocessor 15 [noise] whereas, here I said that it is [noise] 10 and 11 they remember correctly So, [noise] this co [vocalized-noise] coprocessor 15 is reserved for MPU MMU [noise] and cache controller also [noise]. So, what [noise] [vocalized-noise] that I am also saying that MPU is [noise] connected as address bus [noise], but in the VFP case, it was not connected to address bus, but only to the data of bus

[noise] Whereas, in case of MPU or MMU they need to be connected to the address bus because they are something do will be transfer of translation address that is MMU is done ok I will talk about that later, but MPU is job is to protect the [noise] memory accesses [noise] ok, different area of memory it wants to protect it. So, that is a functionality of MPU with I will go into detail now [noise] So, if you chance to perform a job of protecting your memory accesses you should know what the ARM processor is protect ok. So, as I mentioned earlier the address generation is with the ARM processor, nobody is going to control that because our instructions which are getting executed in ARM processor only controls how the addresses are generated by the processor, but [noise] the generated addresses can be seen by the MPU or for that matter MMU and then they can read it and do some translation and then then the security can be (Refer Time: 11:01) that MMU means it will transfer to the address will be transfer to main processor you know main memory, in this case the same address bus goes through a [vocalized-noise] main memory, but MPU also looks at the addresses ok [noise] So, and is it required that is needs to be connected to the data bus of course, yes because the MPUs controller are configured through [noise] the coprocessor instructions ok. So, [noise] it may have to transfer some not data that focus instruction should be [noise] you know transferring the content from the register, here to the some controller here and from here to here. So, this MPU and MMU are connected to both occurs in data bus and they may [noise] knew the no they may need the content based on what is happening which instruction is getting executed by the coprocessor. If so so for ARM processor is executing where coprocessor in section which is saying it is fifteen then, MMU [noise] or mm MPU which is there in the system we will become active [vocalized-noise] and then try to understand what is what is that the asked ARM ok. So, this is how the whole thing process [noise] in the [noise] case of MMU [noise] Let us come back [noise] ok. So, let me change the color [noise]. So, I can get over a newer may give understand that, it is not compressing that coprocessor cannot look at the data bus But if it is needed, you can do which can be connected to both address and data bus ok; and [noise] driving the data bus is controlled if we if the coprocessor have to drive the data bus means; that means, it has to writing to something into the memory or that is into the register something as we transfer then that will be controlled by ARM So, ARM will control what the coprocessor will do ok if, but it can be [noise] seen sitting on both address and data bus to [noise] based under functionality of the coprocessor ok. In the case of VFP there was no meaning for you to know the address, what is happening because it was interested only in knowing the instruction. So, it was looking at it ok, but there is no restriction that it needs [vocalized-noise] cannot be connected or something [noise] ok that is that that ah you [noise] have it in your mind. So, that now [vocalized-noise] you [vocalized-noise] when you look at the functionality of different coprocessor you will know that ok Let us see what are the processes look at this processor are something which is running in the processor [vocalized-noise] ok, different context is maintained by the processor. So, if there is a single processor in the system ok, I am not talking about multi processor system it is only two processor then there can be only one process in the processor ok, only one process can be active at a time [noise] just remember the word active [noise] only one process can be running at a time, but it can support multiple processor. So, [noise] if it has to support your processor has to support, multiple processors running then there should some [noise] some software functionality added to the [noise] system ok, it could be a OS or [noise] maybe we can have some other controls with the minimum ah scheduling system and ah minimum process generates creation and process switching all that if it is there then it can be done Let us assume for simply (Refer Time: 14:31) when you are saying a small kernel micro kernel maybe is in the [vocalized-noise] in the system which is getting the control first and then it builss a set of processes in the system ok. So, this is the main memory maybe all the ah processes will be in the memory, but only one will be executed; that means, what [noise] this process related code data and stack [noise] will become active. So, this part of the memory will become active [noise] and then the processor will execute the [vocalized-noise]

process P 1now [noise] After that maybe I will tell you different reasons where this will go back ok and then new process will be loaded. So, this is [noise] you might have and ah know known this of, if you ah undergone an operating system course [noise], but I am not assuming that you have ah good understanding of this ok without the now in indicate I understanding of OS, but as long as you know that what the process name and the how a process can be run on a same processor that much of knowledge is enough to [noise] understand the different features that are provided by (Refer Time: 15:41) MMU and whatever I am with this book today and given in subsequent chapter ok [noise]. So, process is a program execution, [vocalized-noise] the components of processors are the code to be executed, the program to the executed that data the program uses while executing the code ok. And the resources required by the program such as heap or stack see I am I am not [noise] maybe open a goods heap or a moment you know for ah maybe in the beginning at the class something I have been tell [noise] maybe let me tell you what the heap and [vocalized-noise] you know stack means this is ok. This is stack because going downward ok, [noise] this is some memory ok in the main memory this is a heap [vocalized-noise] So, you might have come across now if you are recognize heap program malloc ok [noise] and [noise] you know, this it would have come across this [vocalized-noise] ah particular [noise] ah um function call. That means, it is getting some dynamically allocated memory ok [noise] and then the [vocalized-noise] program uses that [vocalized-noise] memory which will be allocated from the stack oh sorry from the heap. And then what happens it may release the fill the memory [noise] and then it goes back to the heap and then some other time [noise] and some other process or maybe the same process [noise] ok because of this heap it [noise] its all depends on how it is maintained? It is maintained as a OS or it is maintain at the process level So, in that case what happens, if the heap stage will be given [vocalized-noise] whenever it is required and then the program uses it and release it. So, this kind of the heap and stack normally is to ah manage by OS So, they will also be there in the [vocalized-noise] other part of the resources for a process And the status of execution is maintaining the registers and the CPSR values. So, [noise] so when a process needs to be you know moved out of a processor and then a new processor have to come as to come into the system this is a processor for execution; because I am talking about only single processor. Then what happens is [noise] all these things ok [noise] do not think that, every time [vocalized-noise] whole code is coming and sitting in that [vocalized-noise] processor no no [noise]. So, because code will be residing in the memory and then [noise] it is being accessed [noise] whenever it is needed. So, instructions are executed effectively Similarly, data is also it visiting in the memory and here whenever it is needed some data instruction and something is written back [noise]. So, they answer (Refer Time: 18:13) sorry, ah know the whole chunk of the data code is residing in the main memory only [noise] But pieces of that will come to the program processor and then, get executed and then based on the execution the data comes moves between these two. So, when we say during a process is saved [noise] and state is maintained here in terms of registered values or CPSR values those things need to be saved ok So, that is maybe a context [noise] ok, which is maintained by the OS and then on each process there will be a process ID and then it maintains that particular context of a process in its own structure. And then [noise] if next low make sure make sure that a you know one process goes out and the another process comes in So, it will be very difficult to go into details of this [noise] because it will become another [vocalized-noise] operating system goes to I am just stopping with this, I assume ah presume that business of ah introduction is ah if enough ah this particular course from this context of the course ok So, these are the contents are to be go ah concerns with a particular process [noise] So, based on event ok, [noise] I will tell you what are the events [noise] possible event OS may say a state of the active process and may restore the state of a new process we will it state in normal state then the OS system area, where it is maintaining the context of the each of the processes in the systems Because only OS knows need to processes running and which process are residing in the memory as a background job and then which [noise] what state it is all those things ok Now, what the what is the context switch; that means, that switching between one process to other. So, what must get saved on a context switch everything that the next process may damage; that means, if it is going to be modified then it is better to save them. So, program

counter will be change their new program which is coming into this PSW, the program status what will be assessed then the process and any floating point register. So, normally what happens in the floating point is, we do not know suppose there are. So, many processes running in the systems [noise] P 1, P 2 ok, the processor as such know ARM processors does not know or the OS running may not know whether a particular process ok, its going to use the coprocessor or not So, normally what happens is only when a process needs a processor [noise] are enough floating point processor by with all you know now to be specific, then it may [vocalized-noise] be having some coprocessor instruction in it and that will be executed by the process So, normally coprocessor is getting saved into the context only when a process want it [noise] ok its not ah always, but you are sure that every process needs the registers in the processors ARM [noise]. So, that actually saves by default, but coprocessor may be said only when it is needed [noise] ok, just keep in mind ah because I have mentioning here I thought I would just touch up on that So, I sort of memory and codes needs to be knowledge that is saving the processor it has to be [vocalized-noise]. So, that needs to be taken care off ok, it cannot access anything else other than its own area. So, that is where we need the functionality of MPU ok, you may wonder why I am not coming to the MPU at all and talking about process context switch and all that [noise], but you can began is that you should know the intent ok. We should know why we need an MPU before we start learning about what is inside. So, it is needed then we have multiple processes running in the system and, multiple processes they have their own code and data. So, when a particular process is running suppose P 2 is occupying the feet here in the ARM processor [noise] it should only [noise] restricted accessors to the code and data of its own area and it will not expect them But can you guarantee that they do, always access only this if a proper process is there is name, but by if there is a you know [vocalized-noise] the implicit ah sorry inadvertent the ah um ah mistake or may be intentional access could happen. So, in that case what happens it will may intentionally try to access the some other part of the memory. So, during that time we are there should be some provision that is supported by hardware to protect it from access from other processes ok. So, that is [noise] what we are timing will coming to [noise] ok Add some a some file access if (Refer Time: 23:13) support file ah [noise] management unit ok [noise] for file system [noise] ok [noise] Scheduling and context switch. So, any process may give up the CPU ok, give up the CPU may its may willingly wants to go out of the CPU, but performing IO operation when it that is the IO operation, OS gets the control because our IO operations are managed by OS [noise] ok, why? [noise] I will give one example suppose [noise] P process P is there and processor P 2 is there both of them are [noise] trying to output onto a serial code ok [noise] ah um call it a UART [noise] ok. This is a peripheral device and we the we can write it into this and then the characters will come out and suppose you are connected into a PC [noise] ok [noise] ok PC is there [noise] and showing the word UART into it is there ok [noise] So, if it is handle to the serial both the data will come here, [noise] now suppose P process P 1 has put some hello word [noise] ok and in between in this scheduled out and then P 2 get the control of ARM ok ARM processor [noise] Now P 2 also tries to write into ur So, as you know where [vocalized-noise] now hello word could have been written into some buffer and then the ur to is trying to put it into the serial code it will take [noise] its own switch times because of the bar rate So, you will get [noise] if it is ah no name 96, 100 dot rate, it will take no hello data prime compared to the execution scheme. So, the tatters maybe hello word or maybe hello as some word has not come then P 2 as v 2 also a (Refer Time: 24:55) sending some characters out and it is writing ah um maybe how are you

Now what will happen hello will come then, how are you will start from because it is directly accessing it and it may [vocalized-noise] the buffers or it may stop this buffer from [vocalized-noise] you know it may overwrite it will do it. So, that now whatever for P process P 1 want a [noise] that may get over in time [noise]. So, we should not allow the processors to access the peripheral [noise] directly, there should be some controller that is OS [noise]. So, that you can order the sequence of accesses [noise] and the suppose, if it is busy with the previous one it may holds the processes something like that. So, there should be some protection [noise] ah that OS will be [noise] in the protection So, in the [vocalized-noise] in this case what happens is, then this is executed OS gets a control because it is waiting for a character to be [vocalized-noise] now entered by the processor, I know from user this process may have to wait for long. So, that time what happens is the OS might bring in another process to a execute [noise]. So, this maybe one of the reasons of here new process to come into the processors, [noise] maybe if the process wants to wait for some even to happen; because some buffer to be very free or it may said that, I want to sleep constant second the process needs to wait for ten second; that means, what a new process can come into the processor. So, it will give up the CPU or it can wait for a device interrupt to happen maybe just a given a file access and then, waiting for the file to be copied by the DMA to the memory before it can do any useful work and it can terminate itself they say that ok exist or now ah it may execute something to fill itself So, in that case the process will terminate by itself. So, these are the reasons where your process may go out of the CPU and a new process may come into the CPU and then other one is OS can forcibly schedule it. So, there are some scheduling mechanisms where [noise] each process is given a time slice ok for each process to run [noise]. So, OS may decide that ok your time now ten millisecond or whatever is read over. So, this has to both and then now new another process very need to may come So, this kind of our priority in a new process with a higher priority has become ready. So, whatever may be the data base low priority it should be thrown up and then a new higher priority process will come up [noise] On a page fault the [vocalized-noise] current processor at their you know access something and page fault has obtained ok Then also there are possibility of a new process coming. So, whenever when [vocalized-noise] when you give up the CPU means what are mean switch the current process out and gets an another process in [noise] that is what is the job of the OS ok. So, [noise] this is a different scheduling concept, ah just start I will just give a high level overview of OS ok Now, let us [noise] go into more detail what is required for us in the MPU, now typically now if you are geometrical of lower address and by these a higher address ok, because they are assuming that high lower addresses which are having the system memory ok. The system related and code and data and then, given the interrupt vectors ok IVT [noise] inter vector table its also part of the system [noise]. So, they are all deciding in one part of the memory ok and then the user program will be running here [noise] ok, this is a typical [noise] scenario how the layout of memory is used by ah [vocalized-noise] by an operating system living along with the user programs ok [noise] So, it could be that interrupt one process there are multiple process, the [vocalized-noise] a job and ah tasks a process buffer you know in our the second day update maybe if you go into the detail of ah particular OS it may be differ, but at this moment we are not bothered about those details. So, different processes may be occupying different parts of the memory ok that you should know ok So, the CPU is multiplex among them [noise] there is a single CPU shipping ok, ah [noise] CPU and the processor RMP that will made what I mean by that is the ARM processor [noise] ok. Course which is used [noise] by all of them [noise], but in terms [noise] one ah once I will use it then the one job will go out and another job will come and it will be executed when I say it is using may that job is getting executed [noise] ok, [noise] those instructions are getting executed by the data processor. And then it will now keep it here with the help of OS of course, and then the new process will come in [noise] and then they will (Refer Time: 29:25) ok So, this is the context. So, that we understand the protection requirement, now [noise] I am going into little more details as I mentioned to you our lower addresses are here ok, sometimes it is drawn like this and then sometimes like to the lower at a goes down and then like a higher address there. So, you may get confused [laugher] which is low and file flow, I am maintaining it ah for your clarity ok, let us change the color ah take the blue color [noise] ok. Now what happens here this is the OS ok, this factor is a scheduler actually OS. [noise] Now there are multiple processes

which are, already in the system ok, [noise] who created the process? OS creates the processes and they are all be (Refer Time: 30:13) [noise] Now, there are some ah access rights defined So, here you see a process A when while executing you know that it can execute a branch with a offset right, branch with the offset ok or with level branch with link register and then what happens? It is moving to a another address the instruction [noise] execution moves to another address and then it starts executing from there. Now this address, cannot be map to [noise] [vocalized-noise] where a location [noise] or an area of memory which is meant the other process [noise] ah ok In the sense if it is not allowed to execute ok, especially [vocalized-noise] in our execution may not be allowed ok [noise] But sharing of data is allowed ok there are some ways ah [vocalized-noise] you can share the data between multiple processors. So, that is why that time we may have a shared memory which is in the system and ah we allow A process, then in that case you know this may not be a part of this process [noise] B this area it may be ah a shared memory between B and A. In that case it may allow the success [noise], but code access is not allowed [noise] ok. And some places many be data access also may not barrier because process A and C they do not have anything in common they are not as executing anything you know for a particular common application. So, they may not talk a share any data between them so it is not allowed So, that kind of a restriction maybe there, execution will be reduct now access a restriction or even data access ah restriction and then maybe you may also have some kind of a ah um [noise] what are the memory of OS maybe data allocation ok may be accessed by [noise] the processors because, if it wants some support of OS, it will do it to calling the system points ok, that is why we call a system points So, it may not access it directly it will access the OS calls which will allow, [noise] your process to use some of the resources semaphore or even [vocalized-noise] any rocking mechanism ah (Refer Time: 32:37) no any OS features can be accessed. So, this way we have to protect the OS or support from your X are the processor and then we have to protect each of the processor from other processors running in the system. So, these are all can be done with the support of the processor that is what we are going to clean up how it is implemented Now, let us see what are the protected systems are [noise] there are two things; [noise] shielding a system resources, when I say resources mean it would be memory operator and other tasks, from unwanted access is called protection Other tasks means the process area of the or other tasks [noise] from unwanted access is called protection. Now two methods are there one is unprotected system what I mean the unprotected means? It relies solely on software to protect the system resources, [noise] need to have cooperative task for reliable [noise] functioning what I mean by that a suppose I do not have MPU in the system ok, because I do not have space in the soc in this is the very small is soc ok MPU also is a hardware right its accesses some part of the heap So, I do not want MPU I have decided that I will not use the MPU in the system or do it [vocalized-noise] soc with the ARM processes ok. Then there is a that is will be a process will have there are system in report an MPU, but still I can support multiple processes in it provided they are all cooperative that what I mean by that is say, know what your limitations are what your address name is a and then they are all returned well return of course, that matter and they will tested So, that they know why [vocalized-noise] no access inadvertently into the other areas for the process ok. And there is no OS may be OS is there because its multiple processors there a simple small micro kernel may be there to create this processors, but we have to manage it ok. Somehow, without MPU is declared, we [vocalized-noise] we have to have a reliable functioning of this processes to [noise] next just you know this system [noise] want reliably ok But what the advantage we get we get ah you know we there is no overhead of MPU or overhead of protection and other limitation [noise] no hardware intention ah hardware functionalities ah which are complex, they are not there in the system. But it has it has to be [noise] very very cooperative task for a reliable functioning in otherwise they may disturb the normal functionality Now, what is the protected system? Here relies on both hardware and software the protected

system resources ok. I will I will [vocalized-noise] tell you while processor is also needed because that, I told you MPU needs to be configured task ok. Configured in the sense it should be enabled it should be considered which memory is ah having what access which process has its own area and which are the other processors running what is their protection mechanism, all this needs to be programmed into the mpe MPU. Who does it? Using the power process for instruction know MRC and mc are similar to cache we exchange some content into you know from the coprocessor register. And then from ARM register to coprocessor we write something into some register and then gets wide biggest [noise] perfectly, [noise] it starts functioning as its expected to we start protecting the system [noise] So, prior to the MPU enabling the system is open to anybody ok. So, we need some [noise] software, which runs at the beginning and then starts protecting different areas of memory and then starts giving the [vocalized-noise] control to the different processors. So, the software is required to consider the anything [noise] ok that is sometimes that is part of the you know most of the time it is part of the OS job But I am trying to tell you why both are needed and dedicating a; however, enforce resource ownership and restricted access. So, it [vocalized-noise] knows who is the owner of the particular area of memory its controlled by the hardware ok [noise] very good [noise] So, let us change colors for a [noise] ok now protection hardware in ARM ok. What is the hardware [noise]? So, ARM provide several processor equipped with hardware that activity protects the system one is MPU, I told you MMU I mentioned that a MMU includes MPU on stand here [noise] ok, MPU provide hardware protection of several designated regions So, we [noise] I told you the different regions of processors are there the different area of memory is called region ok. I will explain you more about that, [noise] MMU provide protection and as virtual memory capability ok. let us not bother about this, now [noise] because anyway we have the next session talking about that [noise] ok Now, let us give few a overview of you know [noise] what all systems have MPUs, ARM, CPUs which are used in embedded systems, [noise] with this fixed our controlled application program do not require a full MMU [noise] ok. So, suppose if we decide this is the area of particulars you know fixed memory is limited ok and, when the number of processors running is also limited fixed ok. We are not going to dynamically create more processor and then try to look for stage So, in that case what we can do is we can in the memory we can allocate some different locations of the memory for different processes and then, [noise] and then [noise] maybe we need MPU functionality. So, that the protection is done the hardware and we can start executing this code multiple processors, will do in this system and there will be reliably running as long as the number of processors are fixed [noise] And the area that they are going to use [noise] are also fixed [noise] and these are all controlled applications program ok [noise] That means it is not going to go in terms of five in terms of this pair no memory requirement [noise] and then, [noise] the functionalities are all well defined So, in this kind of scenario we can do away with MMU [noise]. So, for such system a simpler MPU is adequate. CPUs which are the CPU that is ARM, CPUs, CPUs, MPUs are [noise] this and this [noise] ok. We let me give you the overview now [noise]. So, these all are the [noise] not to ah advance versions of ARM [noise] ok. And when I talk about the whole [noise] soc is a CPU, if I talked about only the code it is a processor ok if you remember So, CPU is the bigger problem. So, these are all [vocalized-noise] you know [noise] different codes inside that C you know CPU. Now they may have number of regions most of them are 8 [noise] ok, which are either can be considered separately as instruction and data or [noise] the region the regions are memory region which can be considered separately as instruction

region and data region or they cannot be ok Its a common [noise] area for both instruction and data ok no no is there for this code But there is one [noise] voltage unit which is 940 there is a 16 code, but still [noise] the numbering of this regions are always zero to seven ok. I will be talking about this, but ah ah there will be the instruction region, which you are varying from zero to seven and data regions which varying so zero to seven So, what I mean by region a region is the some part of the memory ok. So, how many such regions I can have 8 regions, we can have in the ARM processor and ah some can be identified that it is a instruction region some can be identified data region So, let us not worry about this things there you know because these numbers and the things will we know its not the [vocalized-noise] you know, you can always [noise] look at the manual to understand them ah you do not need to much and much ok [noise] So, what you need to know is at a higher level? Some [noise] 8 or 9 940 has this you know upper for both instruction in data (Refer Time: 41:11) point here ah and as a different two regions. And there are these two we will have a limited zero and seven, 8 regions [noise], but you can choose ok 0 region is, ah you for instruction there stop it for data arrangement [noise] we can consider here. Whereas here we cannot even identify a region is a data region, they are only featured as a region single region ok [noise] very good Let us get into MPU [noise] ok. So, two major classes of resources that need to monitoring that is memory system and peripheral right So, I will give a name memory and [vocalized-noise] peripheral for map to the same [noise] peripherals are also memory map [noise] ok; that means, your peripheral registers also accessed as a memory [noise] and then. So, LDM or SDM or LDR or SDR are used to access them peripheral So, they are all mapping into some part of the memory. So, we need protection for them also are some I produced specifically meant for peripherals [noise]. So, that can be achieved by using MPU So, peripheral your ARM based system generally memory map I told you MPU uses the same methods to protect both the type of resources. So, we does not differentiate between two these two instructions are same ok. And you can define a different attribute [noise] for each of the regiona [noise] ok. I will tell about you know tell you what is [noise] what are attributes are [noise] and ah we can [noise] different regions of the memory can be [noise] take it up separately differently ok [noise] ok What is the region in MPU? An ARM MPU uses regions to support and manage systems protection, your region is a set of attributes; [noise] still I have not told you what a minute processor core holds this attribute in several CP15 registers. So, some attributes are there for each region ok, some memory what are the memory there is [vocalized-noise] another part of a memory they also [vocalized-noise] [noise] there are different part of the memory and they have different attributes [noise] So, these all maintained in the CP15, CP15 is was scope of CP15 which is there. So, the m MPU as I mentioned is really I know implemented as a coprocessor in the ARM system So, identifies each region by a number ok, which ranges between zero and seven [noise] So, I told you [noise] there are eight region So, the numbers are there which are ah um where in some zero to seven at regions are independent of whether the core has a von Neumann or Harvard architecture. So, this is whether it treats data and instruction are a separate or unified single memory does not matter the regions are same for both ok the way it has handle of them [noise] Now, let us talk about attribute, [noise] following are set of attributes. The region is defined by a starting address and the length, let me change color see [noise] every region [noise] is again you are to remember that it is a [noise] part for memory area ok nothing, but a memory area. So, if I make identify a particular [vocalized-noise] part of the memory [noise]. So, suppose it is 0 and this address is may be some [noise] 20000 starting address ok, [noise] this is some 20000 [noise] So, let that ah I am identifying different area in the memory, now you have to mention what is the start address [noise] and then what is the length [noise] ok length or size what I will call So, these two will [noise] exactly tell you what is the start address of the ah region

and what is the end address of the region once you are having two these two parameters you can find out. So, we need this [noise] region is defined by that [noise] Access permission could be any of this [noise]; that means, a particular area in the memory can be both read and write what I mean by that? [noise] If for processor ok, is executing an instruction [noise] when will the read or write will happen only when it is doing some LDM, LDR or STR ok; STR, LDR, but all are lower instructions or store instruction [noise] So, [noise] especially for a data ok; and for ah code area it is the instruction. So, anyway there is no read write for a code area So, first of all [noise] code area ok, has to be read only ok, hardly you will find the reason for it to be a read write right this is understood. Now data area there are two possibilities of data area, one could be [noise] that I want the constant location ok. I store all the constants in the program, const unit of same is in the c program or you want to keep all the const here [noise]; that means, what this is a data area which is maintaining constant values will not be written by even our own program. The programs it will suppose process one is having the owning this address ok, its own range ok we assume that P 1 is having this code also, but that does that does not mean that the process can write it to into a its own code area right, you can read from it, but you cannot write in the code area Similarly, it cannot write into some what are the data area because it is a constant So, here we do not want one run time this area if modified we do not want this to be modified. So, that is why we can say that a some particular [vocalized-noise] data area is read only and then some area we want the data to be written under read and written So, it can be read write [noise] ok, but you may say that some other area is which is not [noise] in same (Refer Time: 47:21) is a P 2 we should be have no answer. So, we need access permissions [noise] which are [noise] one of this, there is no read has you know ah permission like right only ok please remember we cannot be [noise] if you want to write you have to read the process in first to write So, no ARM there will not be any need for only write only [noise] access to a particular package of maintain ok [noise]. So, normally it is not supported ah we do not see that [vocalized-noise] ok And then [noise] a cache [noise] policy, see thus [vocalized-noise] when I spoke about cache I have only talk about cache there are, but suddenly when you [vocalized-noise] when I am talking about MPU cache is running; because cache can be there between a MMU ok cache can be here and then the address may go here as well as it will go to this guy ok and then we will go to memory [noise] ok [noise] So, [noise] sorry [noise] ok [noise], so it is not that while MPU is that cache cannot there cache can be cache can very well be there only MMU it is cannot there. So, cache can be there, in that what happen we need to [noise] have some features attributes these are related to cache why? We are talking about [noise] memory attributes ok. So, we can associate some part of the memory their region, whether it can be cached ok or whether it can be yeah right to do policy or write back policy ok This kind [noise] of a different [noise] [vocalized-noise] properties can be there [vocalized-noise] for a particular region of memory if the system suppose cache also. So, [noise] because we are talking about memory, memory might have this system may have a cache. So, we need to have a the feature supported in the MPU so that if the cache present [noise] then we can [noise] assume how to we can now consider the MPU. So, that cache is also behavior is also managed [noise] that is very important to having 9 And then similarly right buffer can be there it can be as I told you this this is the people which writes into the memory ok, write buffer we talk about it in detail So, if there is a write buffer now I whether it can go through a buffer or not that is a decision, which you can buffer [noise] controlled

access based on processor mode, this is a another thing which I am not produced a ARM processor. As you remember it has got as user mode then supervisor mode, [noise] system mode is a [vocalized-noise] or system mode and then, there are FIQ, IRQ abox all that we start. And if you remember recall this these are all supervisor mode ok, which of is one bank registers ok [noise] and then system mode have a the function set of supervisor mode ok, but if the it is a suggest in register set of user mode [noise] So, there are some control things coming out of the processor which will give you indication of [noise] nopc [vocalized-noise] then it will give you indication of whether it is a supervisor mode or user mode So, term protection can be given the privilege system may given based on the mode this is very important because, normally OS will be running in the supervisor mode [noise] ok And then the all illusions programs will be running in user mode ok, then we can easily protect the OS code. OS code will be accessed only by the supervisor code we just be OS [noise] ah [noise] code, which is running only in the supervisor mode. Whereas, the user processes may not be able to access them So, [noise] MPU has to know which mode the processor is in [noise] ok Now, what are the rules for regions [vocalized-noise] there are several rules that govern the region [noise] regions can overlap [noise] other region. So, I can have a region I prefer I would ah saying you [noise] your region is not overlapping with the other one; now suppose I can I am given a freedom to define a region with the overlapping ok. So, there is a main memory [noise] and there can be a region with a overlapping with detail these two are one region and this [noise] is another region So, this there is a overlap [noise] there is a confusion. Now [vocalized-noise] if overlap region is where how that it behaves I will explain [noise] you then you will understand that [noise] Regions are assigned with priority number that is independent of the privilege assigned to them. So, privilege mode is user are privileged mode ok, but priority number is defined ok that is a region number which we are giving [noise]. So, if the number is higher then, it is highly higher privilege to zero to seven are the region. So, this will be privilege you know priority is higher than this, but privilege is different privilege, [noise] if whether user mode or privilege mode whether the processor is in each mode it talks about that [noise]. But you can have a region with a higher priority number given to a user progress ok, [noise] similarly we can have a lower one given to the kernel process ok step relates process So, I will explain you that concept content context then, we will [noise] know then regions overlap the attributes of region with the highest priority number take precedence. That means, if I have I will explain you if if the priority number is higher then, that is adding a higher precedence; that means, what in the overlap region suppose two regions are overlapping, I told you ok there are two regions overlapping in the [noise] in this place ok Now, suppose ARM processor is giving an address which is calling under this region, [vocalized-noise] which will not know whether to take this [vocalized-noise] attribute are can it take this attributes belonging to this, this case what happens is if this region happens to be 3 [vocalized-noise] and this region happens to be 0 track numbers, then the attribute belonging to 3 will be considered and taken for this What I mean the attributes ah for this [noise] means, where what kind of a cache behavior what are the write be[havior]- write buffer we can enabled or not or [noise] ok; this kind of ah a different ah properties of the region are as per this region. Because this we do it when its two regions are overlapping, the regions number with a higher priority numbers attributes are considered as long as it is increasing that region whereas, one of the memory access is happening within this overlap region Once it comes here it will go to this attribute once address access is happening here this attributes should be used by the processor [noise] So, the priority only applies over the address within the overlap region ok [noise] Some more rules [noise] the region starting address must be multiple of its size, suppose I will tell you the size is a four k [noise] ok, kilobyte the region starting address should also be aligned to 4 kilobyte. That means,

what they are given an address [noise] the 4 kilobyte will occupy how many bits of the address twelve byte each you know now we know ok So, [noise] the address starting address ok has to be mapped ah aligned to this size; that means, all this will be 0 [noise] now what happens? If suppose, if it is a 8 kilobyte [noise] one more bit [vocalized-noise] that is this ok of that also will be 0; that means, the starting addresses aligned on 8 kilobyte So, and the size is also very thick we cannot the arbitrary sizes. So, whatever is the size given there are 6 numbers sizes ah given in the system and we can define on region of that size and then we can aligned on that address; that means, that particular address whatever which that is can also a size occupied all that will be 0 the [vocalized-noise] So, that that region is starting from the aligned address ok [noise] So, region sizes are also any power of two, it has to be any power of two and varying from 4 kilobyte to 4 gigabyte. So, [noise] you should now know [noise] the memory total memory that can be accessed by the processor, [noise] if [noise] 4 gigabyte correct 32 bit [noise]. So, the region [noise] can be of maximum size 4 gigabyte it cannot be more than them ok, you can also define a region which is not covering the whole memory area of a of the processor [vocalized-noise] between that we can define some other smaller regions may be starting with 4 kilobyte ok You can define your region maybe this is 8 kilobyte something like that, you can keep on [noise] defining whatever reasons you need of only new sizes [noise] ok, it will twenty one values you can go to maybe here 1 MB then you will start are 2 power 2 right So, you are starting with a four kilobytes means two power 12 correct then 2 power 13, you know like that you can go on till 2 power 32, [noise] which is a 4 gigabyte. So, only these changes are there possible to define in the at a region you cannot arbitrarily say that 200 kilobytes. I want to define of you cannot ok this is not a power of 2 and [noise] not only these kind of number which are all ah given in the book you can if you want or you can find out yourself on the (Refer Time: 57:51) ok Accessing an area of main memory outside of defined region results in an abort; so, I am not told you how MPU operates, MPU what is that MPU doing suppose you have considered it and then, no I depend the system ok ah um this saying that 0 to 1 gigabyte only is there ok in this memory So, I said that ok all these are all [noise] no accessible, but beyond this there is nothing ok, only one thing can you defined and this is here. Now suppose processor MPU [noise] see gets an address from the processor, which is beyond is one GB; [noise] the MPU will try to see what are the regions are there defined. So, only one region is there which [noise] is assumed that it is a region 0, it checks whether this address with this suppose I am after saying the address which is about it it will see that whether it falls within the defined regions will respect of because I am unable to MPU So, it will be setting for any address is coming from the processor needs to be within one of the regions defined in the system [noise] Because I have defined only one region of size 1 GB and the accurate happens to be more than that something outside this then it will create then get an abort [noise] So, so far I said that only memory abort or data abort or instruction abort comes from a memory unit need not be a memory unit memory unit means it could be MPU also MMU also ok So, now you may get more detail about who will give which abort signal in a processor So, the processor will go to the intervect a table and execute all that here know ah whatever we have discussed earlier all that will happen. So, [noise] MPU is continuously looking at the addresses once it is enabled, it will be looking at addresses have you know going in the know what the processor is accessing both for instruction and data and it will be checking against the region So, its all done in hardware that is why I am telling you it has to be done in hardware because, it is happening every cycle every

m clock cycle, this is happening the comparison of all the addresses and then try to see whether it is allowed or not it needs to be done in the three d cycle. So, you can do it in software again it has to be done in hardware [noise], but you consider it using software and then leave it to the cross MPU to [noise] do its job ok, [noise] I hope this is clear to you, so it could be result in to prefetch or data abort Now, [noise] what are the overlapping region sorely need it ok, I will explain this now overlapping regions occur when some portion of the memory space assigned to one region is also in the memory space assigned to another region. I I will give a example, [noise] so overlapping regions provided up to greater flexibility or assigning different access permission because you have two region. So, you can give two different access permissions to both of them, but how is it giving as flexibility let us see an example ok let me remove all this Now you have a system with the only 256 KB ok, [noise] see this this numbers are chose such a way that that is a two multipurpose ok [vocalized-noise]. So, its very [noise] you should know makes know [noise] even 32 kilobyte is power of 2. So, you see the shaded region the dot share one is privileged access that makes its meant for maybe ox code, why is it given an lower address that is also there is a purpose 0, 0 is here [noise] why is it given 0, 0? [vocalized-noise] Lower address because, intervect tables reside in the lower address [vocalized-noise] ok, there are some configuration configurations possible to keep the [vocalized-noise] you know IVT [vocalized-noise] intervect a table at a I writer, but I am not talking about it this because in the system has only this much memory The intervect table has to be here [vocalized-noise] and it should be protected that is why it is having a privileged access and then, the rest of it is having a user access ok [noise] Now, you see that user access is overlapping with this way also that does not mean this user process will have a free access registers ok, [noise] why it it not have either number here very [vocalized-noise] important if it was reversed. Then what I said just now was possible, but it is chosen very intelligently that region really is given to the user processes to access and then this is the system memory is given a region of one So, [noise] even if the user process is running that are ARM processor will be in a user mode correct, and it is generating an address to access this location by mistake or interest in in considerably. [noise] The MPU will wake up is always awake ok, MPU will look at a I am getting an address, which is overlapping with this region accuracy this region. Now what the processor for job of MPU? It should find out who is having a higher priority number this guy then, whose attributes you should consider for validating whether the success is valid or not, it should take the attributes of this region which happens to be a privileged access. [noise] Then who is prime process now where process, which is running in a user space then create that abort ok [noise] do not allow the access to happen [noise] So, the you the abort handler is implemented by whom by OS, so it will go and see a user process for trying to access it. So, it will not trying to fix every problem and then as I mentioned that doing abort handling it picks up that and execute the same instruction again right. If that was true for normal except where a page is sort or some you know memory where corruption because of some you know, ah that some image state is not available Or basically it is used for virtual memory then a new page that is important to the memory those kind of situation, [noise] the user abort data abort has to restart the instruction whereas, in this kind of cases if you restart it it will again ah in counter then abort because a user process is trying to access a system area So, it will prevent the access and then take appropriate action as per what the OS is programmed to do [noise]. So, this is what the use of that overlapping region Here if you see the region for a region 0, the start and end addresses will be including this particular area ok, you know wonder that why I do? I need to do I can [vocalized-noise] done it some this region to this is the user area right you are free to do it, but this overlapping I will explain you some more ah

But if suppose you are mentioned it like this also [noise] there is no these you know the [re/reason] reason to that concern because this will be protected, that is the one of the advantages the remaining memory assigned to the user space, except for this remainings are [noise] allotted. The privileged region one is given a higher number because its attributes must take decision for the user region [vocalized-noise] So, you are intentionally giving higher number So, that if privilages are over overruling the privileges of this type ok, very good [noise] Now region one is not accessible in user mode though it is overlapping with a region 0 although it is overlapping it does not [noise] mean that this though you can have a an access to this region ok, [noise] this is one of the [noise] uses of overlapping regions Now, I will explain you another one, [noise] take a scenario there [vocalized-noise] this diagram is not showing where the OS is running ok or OS code is maybe I can keep a OS here right everywhere ok [noise] OS will be there, [noise] because its stop the created there must be come kernel somewhere. So, it is doing let us worry about that later Now, see what is happening here, this is the gray you know white area is a users regions ok it has a root user accesses. And there are only two regions regions 0 ok R 0 region ah [noise] 3 will 2 regions are defined ok; this is the higher priority ah higher privilege please remember higher privilege and region 0 [noise] with a three is a region number right. So, it is the higher priority number please there is a [vocalized-noise] priority number is higher that is to a user process ok, if is a it is given with a processor ok Now since the region are restricted to either this or this or only this much area and region 0 has a total area coming under this purview it has got an advantage what is that take a scenario where task one is turning ok. [noise] It is genuine and it is correct if it is generates the address which is within the region ok [noise]. So, will it checked [noise] will it be allowed see region three is higher priority compared to region 0. So, the attribute assigned to this area is belonging to the region 3 attributes this says it is a user process; and if at this range is only this much; that means, when the user process is running where the task one is running [noise] ok. If it by mistake generate intentionally or whatever to access their area belonging to the other task what happens it is not within this region So, even though the region 0 is the lower priority number, because of the restriction in the area the [vocalized-noise] range of address given to the higher priority number rest of it becomes inaccessible to the this step. So, when task one is running it can only access its own area can you get it? It can only has an its own area, if it tries to occur anything outside ok which attribute will become active these region 0 attribute will become active because region three is not covering this region this area. So, region 0 becomes active what does the region 0 said is a privileged access and where what is that you know ah privilege level of the user process it is in a user mode. So, it does not have access to any of this So, the background region indirectly protects the other task areas in the memory see what you are seeing is a memory area ok? Please remember and in a typical system in an embedded system in particular the [noise] there is no hard disk associated. And then, now the processors are not brought in and brought out all those things are not happening, but processes will be switching in the CPU ok Processor may be [vocalized-noise] you know

switching; that means, P 1 will run for sometimes P 2 will run of for some time and then they may be [vocalized-noise] sorting, but all of them are in the memory they reside in the memory each process is residing in the memories prior to the execution OS is occurred when So, you have to protect when this process is running we want to put it the other area and when this process is running we have to put it the other area. So, that is what is achieved by this kind of a overlap or background region So, [noise] we call the the region this as a background region, because that what is active when a particular task window is open ok. Even this task is running this [noise] window area is open, when this task is running only this area is open 5 structure rest of which is protector similarly here. So, this whole thing is protector and only this is accessible So, whereas, when OS comes OS take a control each will be running in which the mode it will be running privileged mode then it will have access of rolling [vocalized-noise] why ok, it will have access because sometimes, none are the process will be running ok OS only will be running. So, this is also not acting. So, now, what happens this whole thing is accessible ok [noise] for the OS [noise] and you can have whatever in [vocalized-noise] So, we what we can do is with [the/this] this background region, we will be able to now collectively can able access to a particularly that what is the [vocalized-noise] another useful feature provided by the overlap region is a background region higher priority region is changing a subset of the background region attributes the higher priority one ten is the ah attribute So, ah maybe you know ah in this scenario ok is a privilege mode ok will not have a access to the task area because once you give the access to the if you are accessing on task area then immediately that region will become active because it is nothing do with the process doing active in the processor once a address term that region gets accurated So, OS will not be allowed to access this region ok ah keep in mind ok, it may have been either once the processes are running, there is no need for a OS who are any controller to access them it is all knowing individually given to the task that is how it is? In this particular scenario that will be just in ah [noise] [ex/access] access restrictions ok [noise] correct Now, shields dormant memory areas from unwanted access when I am now what I mean by dormanted if this task is not active it is dormant So, [vocalized-noise] it has to be protected from other task which is [vocalized-noise] running. Region 3 has a higher priority than region 0 even though region 0 has a higher privilege. So, region 0 has a higher privilege whereas, region 3 has a higher priority. So, any address falling in this category will be controlled by the attributes assigned to the this process [noise] and and ah when we say user see privilege more can access any region ok only user cannot access the privilege mode. So, that way if you are differentiate the accesses to ah different regions in terms of privileges then higher privilege can access other other part of the memory So, that they OS also can have an access So, this all depends on how is implemented ok. So, in terms of privileges there are higher privilege, OS will not have an access ah sorry, ah the lower privilege ah region user processes will not have access to the higher privilege [vocalized-noise] regions. So, that ah kinds of the measure [vocalized-noise] ok Let us quickly see what are the CP15 register with control the MPU? ARM system control coprocessor, [noise] control coprocessor is an on chip coprocessor ok So, the CP15 at that part I will explain you So, it controls the cache controller it controls the MPU, MMU [noise] it controls write buffer it also controls instruction prefetch buffer there is a provision possible that you can have a prefetch buffer in the processor; before instruction for access that can be written in prefetch buffer ok. Branch target cache it will come into play only when branch predicting and other things happening. So, ah let us not bother about that system configuration signals ok you can impact in some of the higher [vocalized-noise] processors Eigen processors of ARM family only I am talking about ARM family

Now, we can even configure the in DNS of the processor is a chip. So, you can change a big family need not be coming from a external signal as where we saw in ARM 7 TDMI. So, this kind of configurations of in DNS can also be controlled by the CP15 register [noise] ok, [noise] the control is effected through the reading and writing the CP15 registers Now, how do you write? And write we know that coprocessor instructions are there the instruction registers are thirty two bits long and then it is access is restricted to only MRC and MCR [noise] So, and only in supervisor mode, so [noise] any of the CP15 instruction can be executed only if the supervisor mode ok; and then only these instructions can be executed till you cannot 0 any other coprocessor instruction like no other no user CDP instruction and then you know ah coprocessor transfer instruction there is a so, many other coprocessor instruction which are data processing and conferencing no come from coprocessor to memory transfer those things cannot be done on CP15 ok, it is implemented such in a way only MCR and MRC MCR and MRC are there coprocessor instruction which can also term ARM register to coprocessor register and ARM coprocessor when I am sorry, coprocessor register to ARM register [noise] So, only these instructions are allowed; that means, you can only configure it and also it has to be in supervisor mode the processor has to be in supervisor mode if it is a decoding a CP15 instruction As that means, the coprocessor instruction with the coprocessor id fifteen use of other coprocessor instructions or any attempted access in the user mode will cause undefined instruction a trap instruction. So, this is the you know he just to recall ah what we saw [vocalized-noise] earlier you know when we discuss about coprocessor instruction So, this is a register of ARM, which can be [vocalized-noise] some value can be put and we can transfer it to a coprocessor of register and the coprocessor registers are there are 2 ok, and then [noise] you know that there are some operation code, [noise] one more operation code is here additional operation code So, in the CP15 were this register is called primary register and this is called secondary register ok. I will ah I will tell you why I am bringing this this we can leave this where MPU and MMU [vocalized-noise] the coprocessors controls, they maintain two levels of [reg/registers] registers and then they associate one register number along a node and then some out find a register are there. For example, suppose see this coprocessor register 0, we will have if small secondary register; that means, it will have another coprocessor register 0 1 2. So, they are all secondary register and this is a primary register see effectively this there should be a space provider in the controller which is behaving there is a coprocessor coprocessor 15 So, when [vocalized-noise] operand operand with the CR 0 comes then it will know that any number mentioned here is actually referring to the another set of registers [vocalized-noise] So, you can always leave with you consider that when you are writing to a CR 0 another CR 0 one condition you can always pass two parameters and then try to write in that So, that is what is being done in implementing the MMUs and MPUs at a coprocessors and cop two is the an instruction. That means, it can [vocalized-noise] put some big patterns here ah sorry here and then you instruct the coprocessor to do different jobs ok, [vocalized-noise] in our sense the it is that MMU or MPU coprocessors ok [noise] Now, there are so many register number these are primary register number ok, [noise] the protection unit has ok. [noise] Another CP should be ok these registers are there ok So, if suppose it was a co [vocalized-noise] at a 14 point processor this number may be you know CP ten ok all those that require normal number given to it it will have its own registers right we saw. So, many registers in the floating point register that is resolved by CP 18. So, it is in a different area different region ok, coprocessor itself as different [noise] register that So, CP15 has the primary registers like this this will be varying from this and the [vocalized-noise] different purposes each of them. So, they have a given different functionalities when you write into this it is controlling the configuration of the system So, that is the way the hardware is designed this if you write at the something it controls the cache controller if we write into this, [noise] it controls the buffer write buffer

writing in the this see is different access permissions for region and then in some writing the some of the registers here. So, control the different regions in the system ok, [noise] region 0 to [noise] seven eight regions can be there and there will be different registers for each of them and you can control their so, [vocalized-noise] then can size of the region. So, different CP15 registers are allocated who has done it ARM ARM has done it ok because there are IP even that ARM. So, they will follow this particular [noise] naming convention and the register number ok So, CP15 register that controls the MPU are MPU are these registers only control the MPU there are MPU related and processor them control the cache also some of them are here some are them control the cache lock down. [vocalized-noise] We saw in the previous sessions these registers control the cache operations. So, this set of registers control only the MPU ok So, how do you program the MPU [noise]? So, if you want to do any region size and location of a region we have to write in to that, I will explain you each of the register how they are ah written into. So, this I am giving an example here see when you are writing this instruction who is executing this [vocalized-noise] instruction, ARM is executing this is why programming. The MPU we execute first instruction and then, we say that ok I am I am just [vocalized-noise] writing into c 2, c 3 c 4. And then, the secondary register happens to be this and then there are other Opcode is no some value I can give 0 or some number and then, from which register in the ARM I am transferring the values it is R 2 coprocessor So, I am this is not transferring some value in a particular register in the form whatever value is here 32 bit value, I am writing into the coprocessor register which primary and which secondary registers we can mention So, an MCR instruction once you do like this it will be embedded into the coprocessor instruction and then put on the it will be executed ok, when actually this instruction goes on the bus actually moves executing it actually the MPU executed ok. There is it will grab it this instruction because it will know that it is meant for it is that know a CP15 and then, it will look at these values and then accordingly it will consider itself So, actually this instructions are fetched by ARM and then actually the job is done by the MPU ok, it is not that [noise] ARM is doing, but ARM has to provide the value ok So, when it is this is [noise] executed this instruction is executed it is transferring the content from R m whichever register it have mentioned. So, ARM has to provide that content out and this this guy will read it that is all, but and then accordingly it will program it (Refer Time: 83:03) ok So, you should know how it is done otherwise we will have always the I mean doubt and the backward domain why is secondary register why is primary register what really happens when you read a book? You may get into all kinds of doubts. So, how we would we understand it? So, you should know [noise] this instructions are actually [vocalized-noise] access from the memory and it is exhibited by the processors ARM processor and ARM, if you know or writing the code would have mentioned [vocalized-noise] R 1 or R 2 and the some proper value would have been written into the there a register and then transfer to this Now, it may be OS code or you may be writing this code and then, then MPU will grab this instruction because it will see the register CP15, we can might for me and then it will read the value from what is coming from R 1 why is execution happens this MCR instruction executed then that value will be taken in by the CPU oh sorry, coprocessor and it will configure itself. So, then based on whatever instructions we give it will be [noise] done ok, I hope this is clear Once you understand this your external dictation, that I am going to do now will be easier Now, you should know how a MPU of this getting programmed that is what we are trying to understand Now using this instructions, which are actually registers on register to coprocessor transfer and we are writing into the coprocessor, [vocalized-noise] which are dedicated for some purposes and it is expecting some parameter to the class which coprocessor will be [vocalized-noise] secondary register. And what operation and which value based on the content of value in stored in the register and what register you are mention here it will get configured ok Yeah it has system control may happen now cache attributes may just written. So, or will may enable the MPU are anything here or will may decide the regions all this things will be happening ok, based on this mention

here ok. What is mentioned here region and size location can be considered [noise] because you need to consider eight region. So, you need to size give a size and the determining you know starting address and the length of the region you have to mention [noise] So, we need a at least one big register to hold that values. So, a dedicated c 0 to c 7, 8 registers are reserved for different regions in the programs [noise] ok and which is coming under pcp PC? So, under PC there are multiple registers maintained inside what inside the MPU at PC [vocalized-noise] where it is maintained? Ok I hope the whole scenario is clear to you [noise] ok So, to configure each of the regions this registers are maintained. So, one small example system setup ok let us go by configuring its ok Now what are the steps involved in doing it see [noise] whatever here given we are going to do it in itself ok; that means, we will first defined a region or number of regions in the memory ok. How many regions are there and what are their addresses starting address and the then or that will be decided by writing into proper register each region one zero to seven you will write this values [noise] and then gives you different access permissions whether your particular [vocalized-noise] region is a read only this is when they read and write whatever you want You can give different regions different read access or access permission whether users more oscillating more all that will be configured using this registers. [noise] Then if there is a write buffer in the system, whether it can be buffered or not whether the data when it is written into the memory can go through the write buffer or it can it means directly go to the memory, that we can enable we will do it using write buffer attributes and then we will say whether it can be cache or not ok A particular region can be cached or whether it is an instruction or data cache and the know what kind of a write policy can be applied on the region. All that we will write after doing all these things know, once you decide all the attributes; and then your consider all of them then only we will come to the system control register this is the separate register [noise] under c 1 there is c 0, we will enable that MPU we will enable that cache all that we will do then what happens the complete system gets back Now, till that point none of them are in its because that is the difference it follow you cannot enable, it and then start deciding what parameters are what attributes to give them there will be a net whole thing which fails So, first to decide what each regions are and how they are going to be behaving what is the behavior we expect all that we decide based on this writing into these register and then we at the end we enable, the MPU till then MPU will not be enabled. That means, there it will not be active it will not look at the address is coming on the bus it will not even recognize any regions So, you can start filling the values left until its enable MPU will be no ah in a government in the state it will not do anything once it becomes active then it will start controlling ok. So, define the size and location first using this register c sixteen ok and then set access permissions for each region using c 2, c 5 then c will please remember it is all under CP 15. So, everything is inside the coprocessor 15 inside that the different regions are there. So, if the registers are there so, there may be now inside a MPU or it could be or captured in one place and then they will be controlling the MPU does not matter. Oh now you how does it matter where is exactly physically located, but we should know that [noise] it is access to CP15 and cache and write purpose are accessed using now controlled using this [noise] ok and then enable are all of them using in a c one register Now, [noise] this is how the region is managed different regions are there they have different physical know their different addresses are now given the starting address and type [noise] and you have a priority number. So, it will encode the priority and then decide what is a highest priority needs to be enabled because you have overlapping region. So, in two regions are overlapping here to choose the highest value and then based on highest priority attribute register will be active ok. Higher priority attributes will be given ok, that will decide whether a particular this active whether it is cacheable or bufferable or whether user mode or ah privilege more access in happening Now, one thing you should remember here, notice it is only taking the top [vocalized-noise]

bits the bottom 12 bits are not only 20 bits ok [noise] this is 20 and this is 12 oh sorry Let me erase this [noise] this is 20 [noise] ok, [noise] 20 bits are there ok. So, that is 20 this is 1 MB ok. So, the accesses are given with respect to this ok and then the regions are verified ok, let me tell you what are the regions at the set and then we will see the details in the next session ok; any address generated by ARM is checked against the region it falls under and the attributes associated that abort the highest priority number access is allowed based on permissions or abort happens ok So, [noise] ah um [noise] in this case near to 20 because maybe all the regions of 1 MB [vocalized-noise] or more ok, if it is the smaller [vocalized-noise] regions then it could have taken the bits of (Refer Time: 91:13) ok very good Now, let us see here you can see that ok 12 [noise] bits are not used only the top 20 bits are ok this 12 bits [noise]. So, only the top 20 bit of address it could be top 20 bit or less than that or we can check always this because this will be 0 ok, where you you must be knowing If I know I told you that the sizes of the regions can start from 4 kilobyte to 4 GB if the regions cannot be smaller than this ok and then, also the starting address has to be aligned to the region size ok. If it is a four kilobyte this is a smallest region you can have in the memory then the lowest twelve bits of the addresses are addressing this So, since I said that the starting address is aligned to this it will also be 0 all will be 0. So, it is enough if you take only the top 20 bits of address and store it in the register that is why you are keeping only this values ok, [vocalized-noise] this is a actually what I am showing is CP15 c 6 register again it could be c 0 or up to c 7 ok based on which region they are trying to program For example, if they are programming your region for the R R region 0 then c 0 register and then c 6 of c 15 will be used. [noise] And if value will be based on what is the region size if it is a 4 kilobyte starting that you know 20000 ok, then top whole bits will be ignored and the remaining addresses this two under will come here ok Now, should be 0 this value should be 0 and then, this number n is ah a here number varying from 11 to 31 actually what it means is two power 11 plus 1. So, it will become 12 is 2 power 32. So, what exactly means this corresponds to 4 kilobyte size this corresponds to 4 GB size. So, you can choose [vocalized-noise] that is why it was mentioning that power of 2 only will be given because you can vary from, 2 power four into two power thirteen 2 power 14 up to 2 power 32 can be given as one of the sizes of the region So, we are deciding the size now that is decide by this five big pattern stored here which will be interpreted like this ok [noise] which are the processors So, once you enable it this bit you will make its a then this region whatever address given will be checked against the size, what is mentioned and if the address whatever being access the ARM for center this region then it will pick the attributes associated with this regions 0. So, that it is c 0 suppose it will be associated in the region 0 Now, we may wonder there are the attributes of region 0 it is not clear it is only this particular register holds only the region size and location ok. So, there are some other registers used for that [noise]. So, I have explained you this the n is very composed they locate a 4 in GB and the region size and starting address are determined by the memory of your system ok. So, we decide this on a memory map and where you want to use a particular region for what purposes ok access permissions [noise] Now, that is used by this registers where ok c 5 and c 0 here you do not need a separate register for each region like what we uses

for a starting address and the ah size in the previous [vocalized-noise] cases. Now we are trying to are know set one by one, region size is done not you are trying to get the access permission of each region, we want to initialize that is done by using this register [noise] and this is the big pattern used for each chapter ok [noise] The first two this term use for ah region 0 this is for region two one like that and then what are the number know will 0 means no region 0 for under this where different values. And then how are we giving it we are giving different access permissions to it as I mentioned supervisor may have a read write permission for all the regions where a user may have a restricted access to some of the regions ok So, the typical example could be a restricted system resources [noise] you may want no access at all to the user only for the user, supervisor system configurations maybe user person wants to know what inside the software are now where the cache there or not maybe no that is not you want to take some [vocalized-noise]. So, maybe you want ah a some configuration registers to be accessed by the user, but you do not want the user to write into it and then correct the configuration So, we will only provide read only permission to that you can you can use it ok, its not that you need to provide that permission at all, but you can use it this can [vocalized-noise] kind of a configuration for a user region wherever they want to accept a system configurations ok. So, you provide only read only access to the user, but [vocalized-noise] read this supervisor mode here we want rewrite the both, but that does not mean that user can go on write anything in to it in limited region of limited part of the supervisor now where here can be access access to the user because we want some shared system resources ok ah with a user area. So, those kind of things we want to ah give this kind of a permission ok [noise] ok [noise] See here user area only is given a user now we write, but not you know a user may not have a read write for good ah supervisor region, because it has to be in a superior region supervisor mode for is to do a read write otherwise now in both. Now [vocalized-noise] in this region, we have both the supervisor accuracy both user also have a read write [vocalized-noise]. So, basically you may give it for a user area their user processor wants to have a access [noise] the system areas will be in this region ok, we will give this access position. So, that this we this as an access maybe some part of it may be read only where OS normally will be here [vocalized-noise] we will not want to user to access at all only some shared resources we may user accessory, but for [vocalized-noise] for a typical OS code we will give this region attributes access permission So, what I am trying to say is suppose you have a region 0 ok given to the OS area ok, OS area then you have to decide with access permission you will give to a OS area you have to choose this. So, that user has an more access to it and supervisor has a rewrite access to it got it and we will defined a here no stock on the end are you know length [vocalized-noise] in that case, it will be restricted access only OS will have access supervisor user will not have whereas, if you are [vocalized-noise] you know user process area. You may give which one you may give this because, you want a new complete read write access for the user data area this one data area for a code maybe you with you user code area you will give this access, because user should not even user processor should not write into your own code area. So, you make choose you could read only. So, these are the ways you will decide [noise] So, cache and write buffer [noise] this is the cache and write buffer behavior for a particular region. So, we can decide to do ah [noise] one bit for cache ok one bit for cache or each region and then one bit for buffer and then write buffer. So, we can decide whether it is a not cached or not buffered or not cached buffered or cached with the write through policy or cached with the write back policy. So, your region of memory can have a different cache properties and [vocalized-noise] will buffering property So, what are the typical scenario we may give ah write this, this one we may give for a thirty one which one suppose you want to give a region 0 is to be considered for this purpose then you will set both of them to one ok, you will set both of them to one ok you see this so that region, 0 will become write step write through back cache ok. And if you want in a peripheral region, you want you not cashed

and not buffered you will [vocalized-noise] write a 0 0 in that region. Suppose [vocalized-noise] region seven is results are you know maps to the peripheral area we narrate a 0 here ok, that is the way it is configured Then finally, you will enable them last process is to enable the region as selected hardware first of all regions can be there in the system, but it was it will [vocalized-noise] it is not enabled. So, you saw that e was there So, e could be a 0 a region will be designed ok all the parameters will be designed for a region. So, it is not enable at a particular moment and then you can make it active some other defined in time. So, the regions can come and go. So, that can be done by setting this way [noise] easy ok of a particular region that is why I am giving you c 0 to c 7 whereas, here particular MMU or cache or ah sorry MPU this is MPU. So, MPU are data cache or inspection that is the supports do do can caches they will have a different MPU is here and they will may be ah set So, then those cache will be enabled. So, this is the typical example of how to do it ok [noise] Now, I will show you a system which has [vocalized-noise] a small, now I am not ah giving you how to program it, but as you have seen all the register how to write them. So, you will be able to achieve this ok you can take it as an example and then try to write into those registers ok to [noise] realize this [noise] And it is actually in the book also the this reference book now, this has got this particular ah um [noise] page that will given. So, you can verify it also or you can go through that particular example to understand it more ok, to these regions are chosen like this ok a typical example this is the protected area where OS related and the stack there no ah lower region, I will interpret a table will be there and then there are active task task regions are there there is a some stack region which are shared by different processors [noise] and then IO devices peripherals are given some different ah we are known access region So, region four region 3, 2 are the different regions given ok, [vocalized-noise] totally there are 4 regions in the system, but it takes care of the complete area of course, region ok Complete 4 GB memory. So, this will be a typical example I like to to go through the book to see how this is all done. So, that you have a better understanding processor MPU ok further [noise] see another example will be will make your understanding much more clear So, with this we will we are coming to an end of the class now. So, I hope it was useful I enjoyed really sharing this complicated information, but I hope know you are able to follow them and see you in the next class I will next take; bye bye [noise]